SMC Networks ARM PL241 - Manual (Page 27)

Functional Overview
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-7
2.3 Functional operation
This section is divided into:
• AHB interface operation
• AHB to APB bridge operation on page 2-10
• Clock domain operation on page 2-11
• Low-power interface operation on page 2-12
• SMC functional operation on page 2-15.
2.3.1 AHB interface operation
This section describes:
• AHB fixed burst types
• Undefined length INCR bursts on page 2-8
• Broken bursts on page 2-8
• Bufferable bit of the HPROT signal on page 2-8
• Read after write hazard detection buffer on page 2-9
• AHB response signals on page 2-9
• Locked transfers on page 2-9
• Registered HWDATA on page 2-10
• Big-endian 32-bit mode on page 2-10
• Removal of AHB error response logic on page 2-10.
AHB fixed burst types
All AHB fixed length bursts directly map to burst types that the internal interconnect
uses. The internal interconnect and the memory controller are based on transferring
bursts of data. The larger the burst size, the more efficient the transfer and overall
performance. The standard AHB fixed length burst types are directly mapped to the
internal protocol.
Burst operation has performance benefits because when the first beat of a burst is
accepted, it contains data about the remaining beats. For example, from the first beat of
a read burst, all the data required to complete the transfer can be read from memory.
This first transfer has some delay before data is returned. Subsequent beats of the burst
can have less delay because the data they require might have already been read from the
memory.