3 smc set configuration register at 0x1008, Figure 3-8, Smc_memc_cfg_set register bit assignments -8 – SMC Networks ARM PL241 User Manual

Page 68

Programmer’s Model

3-8

ARM DDI 0389B

3.3.3

SMC Set Configuration Register at 0x1008

The write-only smc_memc_cfg_set Register enables the memory controller to be
changed to Low-power state, and interrupts enabled. This register cannot be written to
in the Reset state. Figure 3-8 shows the register bit assignments.

Figure 3-8 smc_memc_cfg_set Register bit assignments

[3:2]

memory_chips0 Returns

the

number of different chip selects that the memory interface 0 supports:

b00 = 1 chip

b01 = 2 chips

b10 = 3 chips

b11 = 4 chips.

[1:0]

memory_type0

Returns the memory interface 0 type:

b00 = reserved

b01 = SRAM

b10 = NAND

b11 = reserved.

Table 3-3 smc_memif_cfg Register bit assignments (continued)

Bits

Name

Function

LQWBHQDEOH

5HVHUYHG

ORZBSRZHUBUHT

8QGHILQHG

This manual is related to the following products:

ARM AHB SRAM/NOR