SMC Networks ARM PL241 - Manual (Page 25)

Functional Overview
ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-5
2.2.1 SMC interface
The SMC interface processes the incoming AHB transfers and sends them to the
command format block.
2.2.2 APB slave interface
The SMC has 4KB of memory allocated to it.
The APB slave interface accesses the SMC registers to program the memory system
configuration parameters and to provide status information. See Chapter 3
Programmer’s Model and APB slave interface operation on page 2-19 for more
information.
2.2.3 Format
The format block receives memory accesses from the SMC interface and the memory
manager. Read and write requests are arbitrated on a round robin basis. Requests from
the manager have the highest priority. The format block also maps AHB memory
transfers onto appropriate memory transfers and passes these to the memory interface
through the command FIFO.
See Format block on page 2-19 for more information.
2.2.4 Memory manager
The memory manager tracks and controls the current state of smc_aclk domain logic.
The block is responsible for:
• updating timing registers and controlling direct commands issued to memory
• controlling entry-to and exit-from low-power mode through the APB interface
• the low-power interface.
See Memory manager operation on page 2-22 for more information.
2.2.5 Memory interface
The SRAM memory interface consists of command, read data and write data FIFOs,
plus a control FSM. To support an EBI, the memory interface also contains an EBI
FSM. This controls interaction with the EBI and prevents the memory interface FSM
from issuing commands until it has been granted the external bus.
See Memory interface operation on page 2-27 for more information.