SMC Networks ARM PL241 - Manual (Page 38)

Functional Overview
2-18 Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
You can change both reset signals asynchronously to their respective clock domain.
Internally to the SMC the deassertion of the hresetn signal is synchronized to
smc_aclk. The deassertion of smc_mreset0n is synchronized internally to smc_mclk0
and smc_mclk0n.
2.4.3 Miscellaneous signals
You can use the following signals as general-purpose control signals for logic external
to the SMC:
smc_user_config[7:0]
General purpose output ports that are driven directly from the
write-only APB register. If you do not require these ports leave
them unconnected. See also the SMC User Configuration Register
at 0x1204 on page 3-19.
smc_user_status[7:0]
General purpose input ports that are readable from the APB
interface through the smc_user_status Register. If you do not
require these ports then tie them either HIGH or LOW. These ports
are connected directly to the APB interface block. Therefore, if
they are driven from external logic that is not clocked by the SMC
smc_aclk signal, then you require external synchronization
registers. See also the SMC User Status Register at 0x1200 on
page 3-18.
You can use the following miscellaneous signals as tie-offs to change the operational
behavior of the SMC:
smc_a_gt_m0_sync
When HIGH, indicates that smc_aclk is greater than and synchronous to
smc_mclk0.
smc_async0 When HIGH, indicates smc_aclk is synchronous to smc_mclk0.
Otherwise they are asynchronous. Ensure that smc_async0 is tied to the
same value as smc_msync0.
smc_dft_en_clk_out
Use this signal for Automatic Test Pattern Generator (ATPG) testing
only. Tie it LOW for normal operation.