Intel 440GX - Manual (Page 55)

Intel
®
440GX AGPset Design Guide 2-31
Motherboard Layout and Routing Guidelines
Because of the specifics of an ATX layout, it is recommended that the PIIX4E component is at the
“END” of the PCI bus, as shown in
Figure 2-28 . This insures proper “termination” of the PCI Bus
signals.
2.9.5 Decoupling Guidelines: Intel
®
440GX AGPset Platform
Decoupling caps should be placed at the corners of the 443GX(BGA Package). A minimum of four
0.1uF and four 0.01 uF are recommended. The system bus, AGP, PCI, and DRAM interface can
“break-out” from the BGA package on all four sides. Additional caps will also help reduce EMI
and cross-talk.
Note: There are other discrete components for V
TT
, GTL Ref Voltages that must be also considered when
routing around the 82443GX.
Figure 2-28. PCI Bus Layout Example
82443GX
PIIX4E
Figure 2-29. 82443GX Decoupling
82443GX
Host Bridge
Controller
492 BGA
0.1uF
0.01uF
0.1uF
0.01uF
0.1uF
0.01uF
0.1uF
0.01uF
v006