Intel Extensible Firmware Interface - Manual (Page 1059)

Glossary
Version 1.10 12/01/02 Glossary-11
PCI Configuration Space
The configuration channel defined by PCI to configure PCI Devices into the
resource domain of the system. Each PCI device must produce a standard set of
registers in the form of a PCI Configuration Header, and can optionally produce
device specific registers. The registers are addressed via Type 0 or Type 1 PCI
Configuration Cycles as described by the PCI Specification. The PCI
Configuration Space can be shared across multiple
PCI Buses . On most PC-AT
architecture systems and typical Intel chipsets, the PCI Configuration Space is
accessed via I/O ports 0xCF8 and 0xCFC. Many other implementations are
possible.
PCI Controller A hardware components that is discovered by a PCI Bus Driver , and is managed
by a PCI Device Driver . PCI Function and PCI Controller are used
equivalently in this document.
PCI Device Driver Software that manages one or more PCI Controllers of a specific type. A driver
will use the PCI I/O Protocol to produce a device I/O abstraction in the form of
another protocol (i.e. Block I/O, Simple Network, Simple Input, Simple Text
Output, Serial I/O, Load File).
PCI Device A collection of up to 8 PCI Functions that share the same PCI Configuration
Space . A PCI Device is physically connected to a PCI bus .
PCI Enumeration The process of assigning resources to all the PCI Controllers on a given PCI
Host Bus Controller . This includes PCI Bus Number assignments, PCI
Interrupt assignments, PCI I/O resource allocation, the PCI Memory resource
allocation, the PCI Prefetchable Memory resource allocation, and miscellaneous
PCI DMA settings.
PCI Function A controller that provides some type of I/O services. It consumes some
combination of PCI I/O, PCI Memory, and PCI Prefetchable Memory regions,
and up to 256 bytes of the
PCI Configuration Space . The PCI Function is the
basic unit of configuration for PCI.
PCI Host Bus Controller
A chipset component that produces PCI I/O, PCI Memory, and PCI Prefetchable
Memory regions in a single Coherency Domain. A PCI Host Bus Controller is
composed of one or more
PCI Root Bridges .
PCI I/O Protocol A software interface that provides access to PCI Memory, PCI I/O, and PCI
Configuration spaces for a PCI Controller. It also provides an abstraction for PCI
Bus Master DMA.
PCI Option ROM A ROM device that is accessed through a PCI Controller, and is described in the
PCI Controller’s Configuration Header. It may contain one or more PCI Device
Drivers that are used to manage the PCI Controller.