Intel Extensible Firmware Interface - Manual (Page 1009)

Version 1.10 12/01/02 J-1
Appendix J
EFI Byte Code Virtual Machine
Opcode Summary
The following table lists the opcodes for EBC instructions. Note that opcodes only require 6 bits of
the opcode byte of EBC instructions. The other two bits are used for other encodings that are
dependent on the particular instruction.
Table J-1. EBC Virtual Machine Opcode Summary
Opcode Description
0x00 BREAK [break code]
0x01 JMP 32{cs|cc} {@}R
1
{Immed32|Index32}
JMP 64{cs|cc} Immed64
0x02 JMP8 {cs|cc} Immed8
0x03 CALL 32{EX}{a} {@}R
1
{Immed32|Index32}
CALL 64{EX}{a} Immed64
0x04 RET
0x05 CMP [32|64]eq R
1,
{@}R
2
{Index16|Immed16}
0x06 CMP [32|64]lte R
1,
{@}R
2
{Index16|Immed16}
0x07 CMP [32|64]gte R
1,
{@}R
2
{Index16|Immed16}
0x08 CMP [32|64]ulte R
1,
{@}R
2
{Index16|Immed16}
0x09 CMP [32|64]ugte R
1,
{@}R
2
{Index16|Immed16}
0x0A NOT [32|64] {@}R
1
, {@}R
2
{Index16|Immed16}
0x0B NEG [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x0C ADD [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x0D SUB [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x0E MUL [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x0F MULU [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x10 DIV [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x11 DIVU [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x12 MOD [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x13 MODU [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x14 AND [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x15 OR [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x16 XOR [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x17 SHL [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x18 SHR [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
0x19 ASHR [32|64] {@}R
1
,{@}R
2
{Index16|Immed16}
continued