Intel MD566X - Manual (Page 128)

56K V.92 Data, Fax, and Voice Chipset
128 Intel Confidential Programmer’s Guide
b) The data ready bit, DR (LSR0), is set as soon as a character is transferred from the Internal Shift register to
the RCVR FIFO. DR is reset when the FIFO is empty.
2) When the RCVR FIFO and receiver interrupts are enabled, the UART initiates a RCVR FIFO time-out interrupt
under the following conditions:
a) A RCVR FIFO time-out occurs when:
— At least one character is in the FIFO.
— The most recent serial character
received was longer than four
continuous character times ago.
— The most recent DTE read of the
FIFO was longer than four continuous
character times ago.
b) When a time-out interrupt has occurred, then it is cleared and the timer is reset when the DTE reads one
character from the RCVR FIFO.
c) The time-out timer is reset after a new character is received or after the DTE reads the RCVR FIFO.
3) When the transmitter FIFO and the transmitter interrupt are enabled (FCR0 = 1, IER1 = 1), the UART initiates
XMIT interrupts under the following conditions:
a) The Transmitter Holding register interrupt (IIR = 02) occurs when the XMIT FIFO is empty; it is cleared as
soon as the transmitter holding register is written to or the IIR is read. During servicing, the 1–16 character
interrupt can be written to the XMIT FIFO.
10.2.2 FIFO Polled Mode Operation
Both the modem receiver and transmitter UART FIFOs can be set up for polled mode operation. The UART FIFO is set for polled
mode when FIFOE (FCR0) = 1 and the respective interrupt enable bit (IER) = 0.
In polling mode, the DTE checks the LSR for receiver and/or transmitter status. The LSR register provides the following
information:
• LSR7 indicates when any errors occur in the RCVR FIFO.
• TEMT indicates when both the XMIT FIFO and Shift registers are empty.
• The THRE bit (LSR5) is set to ‘1’ whenever the XMIT FIFO is empty.
• LSR1 through LSR4 specify when a break interrupt, framing error, parity error, or overrun error occurs.
• The DR bit (LSR0) is set to ‘1’ as long as there is at least one byte in the RCVR FIFO.
Unlike FIFO interrupt mode, FIFO polled mode does not support buffer trigger levels or time-out conditions