FUJITSU MCE3130AP User Manual
Page 77
C156-E142-02EN
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4.3.1.9 ATA Features register
This register is used for the SET FEATURES command.
4.3.1.10 ATAPI Features register
This register's bits are defined as shown below.
Table 4.11 Bit definitions of ATAPI Features register
7
6
5
4
3
2
1
0
Reserved
OVERLAP
DMA
Write
! All values in bits 7 to 2 are ignored.
! OVERLAP is ignored.
! When DMA is 1, the ODD performs DMA transfer for data.
4.3.1.11 ATA Sector Count register
This register is used for the SET FEATURES command.
4.3.1.12 ATAPI Interrupt Reason register
This register's bits are defined as shown below.
Table 4.12 Bit definitions of ATAPI Interrupt Reason register
7
6
5
4
3
2
1
0
Reserved
(0b)
Reserved
(0b)
Reserved
(0b)
Reserved
(0b)
Reserved
(0b)
RELEASE
IO
CoD
Read
! A value of 1 in RELEASE indicates that the ODD released the ATA bus before completion of
the current command.
! IO indicates the direction of data transfer. See Table 4.13.
! CoD indicates the type of transfer. See Table 4.13.