Endura RADISYS KP915GV - Manual (Page 43)

KP915GV Product Manual
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• Support ASF1.0 and 2.0 alerting
• Support Wake On LAN (WOL) and ACPI
• Programmable LED functionality
• On-chip power control circuitry
• Loop-back capabilities
• IEEE 802.3ab Auto-Negotiation support and PHY compliance with compatibility
• Package 15x15 mm 196 pin TF-BGA
3.3.4 Super I/O Interface
The motherboard is designed to support the NS PC8374K controller. The Super I/O provides
support that includes floppy, PS/2, serial port, and parallel port to rest of platform through the ICH6
via the Low Pin Count (LPC) interface.
Serial Interfaces
Power Management
LPC Bus
PS/2 Interfaces
Floppy Drive Interface
Parallel Port Interface
Infrared Interface
KBC Ports
PWM
Tacho
GPIO Ports
Reset
Logic Power
Supply
LEDS
SMI
Vbat
South Bridge
FLOCK
SMBus I/F
Drv(3)
System
BIOS
PC8374K
FAN(3)
Figure 10. PC8374K Block Diagram
3.3.4.1 System Health Support
• Fan Monitor and Control
• Three PWM-based fan controls
• Four 16-bit resolution tachometer inputs
• Software or local temperature feedback control