Endura RADISYS KP915GV - Manual (Page 112)

KP915GV Product Manual
112
Prescale 4-bit value to set the watchdog counter period
0..15 16..1s period (a value of 1010b gives a period of 6 seconds)
1 Description
RES Reset after second timeout:
0 No reset
1 Force system reset after second watchdog timeout
SMI Generate SMI after first timeout: 8
0 No SMI
1 Generate SMI after first watchdog timeout
WEN Watchdog enable:
0 Disable watchdog timer
1 Enable and start watchdog timer
8 Use of this feature normally requires a custom BIOS – contact RadiSys for more information. The
standard BIOS does not route the SMI and thus ignores the event – causing a system reset after
the second timeout unless the timer is restarted.
B.3 Watchdog Kick
7 6 5 4 3 2 1 0
Don’t care 1
W W W W W W W W
I/O location: 066h
Index 0
Default: 00000000b
B.4 Watchdog Status
7 6 5 4 3 2 1 0
Prescale TO2 TO1 WEN 0
RO RO RO RO RO RO RO RO
I/O location: 066h
Index: 0
Default: N/A
Prescale 4-bit value to set counter period (copy of data written)
TOC1 First timeout:
0 First timeout has not occurred
1 Timer has expired at least once
TOC2 Second timeout:
0 Second timeout has not occurred
1 Timer has expired at least once
WEN Timer enable:
0 Timer is disabled