Sundance SMT950 - Manual (Page 6)

Version 2.0 Page 6 of 52 SMT950 User Manual
Figure 8 - Clock Structure. .....................................................................................................18
Figure 9 - External Clock........................................................................................................19
Figure 10 - Clock Architecture Main Characteristics. .............................................................20
Figure 11 – Mezzanine module Connector Interface (SLB data and power connectors).......21
Figure 12 – Mezzanine Module Interface Power Connector and Pinout. ...............................23
Figure 13 – Daughter Module Interface: Data Signals Connector and Pinout (Bank A). ......24
Figure 14 – Daughter Module Interface: Data Signals Connector and Pinout (Bank B). .......26
Figure 15 – Daughter Module Interface: Data Signals Connector and Pinout (Bank C). .......27
Figure 16 – Setup Packet Structure. ......................................................................................28
Figure 17 – Control Register Read Sequence. ......................................................................28
Figure 18 - Firmware Block Diagram......................................................................................47
Figure 19 - Space available in FPGA .....................................................................................48
Figure 20 – Main Module Component Side............................................................................49
Figure 21 - Main Module (SMT368) Solder Side....................................................................49
Figure 22 - Daughter Module Component Side......................................................................50
Figure 23 - Daughter Module Solder Side..............................................................................50
Figure 24 - Connectors Location. ...........................................................................................52