Sundance SMT950 - Manual (Page 47)

Version 2.0 Page 47 of 52 SMT950 User Manual
FPGA Design
The following block diagram shows how the default FPGA design is structured:
SLB SMT368 Virtex-4 FPGA
Comport
Interface
Registers
ADCA Serial
Interface
ADCB Serial
Interface
DAC Serial
Interface
Clock Serial
Interface
Temperature
Serial
Interface
Route and
Format
Route and
Format
SHBB
Interface
SHBD
Interface
Trigger Block
SMT950
Other
Sundance
Module (DSP
Module
Usually)
DACs ChA
and ChB
data port
ADCs ChA
and ChB
data port
2x14 bits
2x16 bits
Ext. Trigger
ADC A&B
and DAC
A&B
ADCs ChA
SPI
ADCs ChB
SPI
DAC SPI
Clock SPI
Figure 18 - Firmware Block Diagram.
Serial Interfaces
All serial interfaces have been designed in accordance with manufacturers
datasheets and validated by probing and checking against timing provided.