Sundance SMT950 - Manual (Page 35)

Version 2.0 Page 35 of 52 SMT950 User Manual
DAC Register 4 – 0xC.
For more details, refer to DAC5686 datasheet.
DAC Register 4 – 0xC
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Ssb Interl Sinc Dith Sync Phstr Nco Sif4 Twos
Default ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
1 Dual_clk DSS_gain[1:0] Rspect Qflag Pll_rng[1:0] Rev_bus
Default ‘0’ ‘00’ ‘0’ ‘0’ ‘00’ ‘0’
DAC Register 5 – 0xD.
For more details, refer to DAC5686 datasheet.
DAC Register 5 – 0xD
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Daca_offset[7:0]
Default ‘00000000’
1 Daca_gain[7:0]
Default ‘00000000’
DAC Register 6 – 0xE.
For more details, refer to DAC5686 datasheet.
DAC Register 6 – 0xE
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Daca_offset[10:8] sleepa Daca_gain[11:8]
Default ‘0’ ‘0000’
1 Dacb_offset[7:0]
Default ‘00000000’
DAC Register 7 – 0xF.
For more details, refer to DAC5686 datasheet.
DAC Register 7 – 0xF
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Dacb_gain[7:0]
Default ‘00000000’
1 Dacb_offset[10:8] sleepb Dacb_gain[11:8]
Default ‘000’ ‘0’ ‘0000’