Sundance SMT950 - Manual (Page 18)

Version 2.0 Page 18 of 52 SMT950 User Manual
Figure 8 - Clock Structure.
ADCs can both receive the same clock or the fraction of the CDCM7005 input clock
(/2, /3, /4, /6, /8 or /16), the maximum being 125MHz for each ADC. This input clock
can be coming from the on-board fixed VCXO or from an external source. Here is a
list of possible sampling frequencies for the ADCs:
ADC Sampling
Frequency
CDCM7005 Setting Clock source
Not Allowed /1 On-board VCXO (fixed
245.76MHz)
122.88 MHz /2 On-board VCXO (fixed
245.76MHz)
81.92 MHz /3 On-board VCXO (fixed
245.76MHz)
61.44 MHz /4 On-board VCXO (fixed
245.76MHz)
40.96 MHz /6 On-board VCXO (fixed
245.76MHz)
30.72 MHz /8 On-board VCXO (fixed
245.76MHz)
15.36 MHz /16 On-board VCXO (fixed
245.76MHz)
Anything between 10
and 125 MHz
/1, /2, /3, /4, /6, /8 or
/16
External Clock