Sundance SMT950 - Manual (Page 20)

Version 2.0 Page 20 of 52 SMT950 User Manual
Output Voltage Level 0-2.4 Volts fixed amplitude
Output Format LVTTL
External Trigger Inputs
Input Voltage Level 1.5-3.3 Volts peak-to-peak.
Format
DC-coupled and Single-ended (Termination
implemented at the connector). Differential
on option (3.3 V PECL).
Impedance 50-Ohm.
Frequency range 62.5 MHz maximum
Delay
External Ref. Input to Ext Ref. Out
External Clk Input to Ext Clk Out 9ns (between J29 and J4)
Figure 10 - Clock Architecture Main Characteristics.
Power Supply and Reset Structure
The SMT950 gets two power sources from the base module: 3.3 and 5 Volts. Linear
regulators are used to provide a clean and stable voltage supply to the analog
converters.
JumperJ1
There is one jumper (3 pin header) on the board. It is to control the power supply of
the DAC internal PLL. When fitted on positions 2 and 3, the PLL is enabled, whereas
on positions 1 and 2, it is disabled. Please refer to the DAC5687 datasheet for more
details.
Green LEDs.
There are 7 LEDs on the SMT950 Daughter Module. Five are dedicated for power
supplies monitoring: LED1 (1.8V DAC), LED2 (3.3V Clock), LED3 (3.3V DAC), LED4
(3.3V ADCA), LED6 (3.3V ADCB) should be all ON when the board is under power.
They state that power supplies all work fine.
LED5 (ADCs) should be flashing once the ADC Clocks are set up. It is actually a
divided version of ADCA sampling clock). LED7 (DAC) is a divided version of
PLLLOCK coming from the Dac (DAC5687).
Mezzanine module Interface
The daughter module interface is made up of two connectors (data and power). The
first one is a 0.5mm-pitch differential Samtec connector. This connector is for
transferring data such as ADC or DAC samples to and from the FPGA on the main
module. The second one is a 1mm-pitch Samtec header type connector. This
connector is for providing power to the daughter-card.