Sundance SMT950 - Manual (Page 30)

Version 2.0 Page 30 of 52 SMT950 User Manual
0x24 DDS Register 4 – Step Phase Increment LSB Read-back (FPGA Register) DDS Register 4.
0x25 DDS Register 5 – Step Phase Increment MSB Read-back (FPGA Register) DDS Register 5.
0x30 DAC Register 0. Read-back (FPGA Register) DAC Register 0.
0x31 DAC Register 1. Read-back (FPGA Register) DAC Register 1.
0x32 DAC Register 2. Read-back (FPGA Register) DAC Register 2.
0x33 DAC Register 3. Read-back (FPGA Register) DAC Register 3.
0x34 DAC Register 4. Read-back (FPGA Register) DAC Register 4.
0x35 DAC Register 5. Read-back (FPGA Register) DAC Register 5.
0x36 DAC Register 6. Read-back (FPGA Register) DAC Register 6.
0x37 DAC Register 7. Read-back (FPGA Register) DAC Register 7.
0x38 DAC Register 8. Read-back (FPGA Register) DAC Register 8.
0x39 DAC Register 9. Read-back (FPGA Register) DAC Register 9.
0x3A DAC Register A. Read-back (FPGA Register) DAC Register A.
0x3B DAC Register B. Read-back (FPGA Register) DAC Register B.
0x3C DAC Register C. Read-back (FPGA Register) DAC Register C.
0x3D DAC Register D. Read-back (FPGA Register) DAC Register D.
0x3E DAC Register E. Read-back (FPGA Register) DAC Register E.
0x3F DAC Register F. Read-back (FPGA Register) DAC Register F.
Register Descriptions
Reset Register – 0x0.
Reset Register – 0x0
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Reserved Reserved DDS
Reset
PHSTR CDCM7005
Reset
DAC Reset ADCs
Reset
Default ‘0’ ‘0’ ‘1’ ‘00’ ‘1’ ‘1’ ‘1’
Reset Register – 0x0
Setting Bit 0 Description
0 0 Normal Operation.
1 1 Resets both ADC devices as well as their corresponding Serial Interfaces.
Setting Bit 1 Description
0 0 Normal Operation.
1 1 Resets both DAC device as well as its Serial Interfaces.
Setting Bit 2 Description
0 0 Normal Operation.
1 1 Resets both CLK device as well as its Serial Interfaces.
Setting Bit 4&3 Description
0 00 Normal Operation – DAC PHSTR is Tri-Stated.
1 01 DAC PHSTR line is driven High.