Sundance SMT950 - Manual (Page 36)

Version 2.0 Page 36 of 52 SMT950 User Manual
CDCM7005 Register 0 – 0x10.
For more details, refer to CDCM7005 datasheet.
CDCM7005 Register 0 – 0x10
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 VCXO_divider[3:0] Reference Divider[9:6]
Default ‘0000’ ‘0000’
0 Reference Divider[5:0] Register Selection[1:0]
Default ‘000000’ ‘00’
CDCM7005 Register 1 – 0x11.
For more details, refer to CDCM7005 datasheet.
CDCM7005 Register 1 – 0x11
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 Freq Detect Manual or Auto
Ref.
Programmable Delay N[2:0] Programmable Delay M[2:0]
Default ‘0’ ‘0’ ‘000’ ‘000’
0 VCXO_divider[11:4]
Default ‘00000000’
CDCM7005 Register 2 – 0x12.
For more details, refer to CDCM7005 datasheet.
CDCM7005 Register 2 – 0x12
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 OUT2A0 OUT1B1 OUT1B0 OUT1A1 OUT1A0 OUT0B1 OUT0B0 OUT0A1
Default ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
0 OUT0A0 Output Signaling Selcetion[5:0] Register Selection[1:0]
Default ‘0’ ‘00000’ ‘01’
CDCM7005 Register 3 – 0x13.
For more details, refer to CDCM7005 datasheet.
CDCM7005 Register 3– 0x13
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 90Div8 90Div4 ADClock Status
VCXO Status Ref OUT4B1 OUT4B0 OUT4A1
Default ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
0 OUT4A0 OUT3B1 OUT3B0 OUT3A1 OUT3A0 OUT2B1 OUT2B0 OUT2A1
Default ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’