Control register settings – Sundance SMT950 User Manual

Page 28

Version 2.0

Page 28 of 52

SMT950 User Manual

Control Register Settings

The Control Registers control the complete functionality of the SMT950. They are
setup via the Comport3 (standard firmware provided). The settings of the ADC,
triggers, clocks and the configuration of the SHB interfaces and the internal FPGA
data path settings can be configured via the Control Registers.

Control Packet Structure

The data passed on to the SMT950 over the Comport must conform to a certain
packet structure. Only valid packets will be accepted and only after acceptance of a
packet will the appropriate settings be implemented. Each packet will start with a
command (4 bits – 0x1 for a write operation – 0x2 for a read operation) information,
followed by a register address (12 bits – see table Memory Map), followed by a 16-bit
data. This structure is illustrated in the following figure:

Byte

Content

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Command

Address 11

Address 10

Address 9

Address 8

Address 7

Address 6

Address 5

Address 4

Address 3

Address 2

Address 1

Address 0

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

Figure 16 – Setup Packet Structure.

Reading and Writing Registers

Control packets are sent to the SMT950 over Comport3. This is a bi-directional
interface. The format of a ‘Read Packet’ is the same as that of a write packet.

Figure 17 – Control Register Read Sequence.