Sundance SMT950 - Manual (Page 19)

Version 2.0 Page 19 of 52 SMT950 User Manual
The same applies to the DAC, with a maximum sampling frequency for clk1 of
250MHz and for clk2 of 500Mhz.
Below is shown how the external clock is fed to the system. By default it is single-
ended and AC-coupled before being converted into LVPECL format. The option of
having a differential external clock is still possible on the hardware by the way of
fitting or not some of the components.
Figure 9 - External Clock.
The main characteristics of the SMT950 Clocks are gathered into the following table.
External Reference Input
Input Voltage Level 0.5 – 3.3 Volts peak-to-peak (AC-coupled)
Input Impedance 50-Ohm (Termination implemented at the
connector)
Frequency Range 0 – 100 MHz.
External Reference Output
Output Voltage Level 1.6 Volts peak-to-peak (AC-coupled)
Output Impedance 50-Ohm (Termination implemented at the
connector)
External Sampling Clock Input
Input Voltage Level 0.5 – 3.3 Volts peak-to-peak (AC-coupled)
Input Format
Single-ended or differential on option (3.3V
LVPECL).
Frequency range 10-500 MHz
External Sampling Clock Output