Sundance SMT950 - Manual (Page 42)

Version 2.0 Page 42 of 52 SMT950 User Manual
The Stop Phase Increment value is coded on 32 bits (DDS Data registers 0x22 and
0x23). Each value corresponds to a frequency generated worked out as follows :
Fout = Stop Phase Increment * F
DAC sampling
(MHz) / 2
32
When the DDS is used in sweep mode, Start Phase Increment should be lower than
Stop Phase Increment
and Step Phase Increment should be greater than 0. When
used to generate a fixed frequency, Start Phase Increment should be equal to Stop
Phase Increment
and Step Phase Increment should be equal to 1.
For Registers 0x22 and 0x23 to take effect, Bit 5 of register 0x1D must be set to 1.
DAC Channel A is the Sine output of the DDS and DAC Channel B is the Cosine
output of the DDS. Both outputs are therefore is quadrature.
The Maximum Phase increment value supported by the design is 0x40000000, which
corresponds to a frequency of 30.72MHz when sampling at 122.88MHz with no
interpolation.
DDS Register 0 – Step Phase Increment LSB - 0x24
DDS Register 4 – 0x24
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 DDS Step Phase Increment [15…8]
Default ‘00000000’
0 DDS Step Phase Increment [7…0]
Default ‘00000000’
DDS Register 5 – Step Increment MSB - 0x25
DDS Register 5 – 0x25
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 DDS Step Phase Increment [31…24]
Default ‘00000000’
0 DDS Step Phase Increment [23…16]
Default ‘00000000’
The Step Phase Increment value is coded on 32 bits. It corresponds to the increment
in phase on each sampling clock cycle (Sweep Mode).
When used to generate a fixed frequency, Start Phase Increment should be equal
to Stop Phase Increment and Step Phase Increment should be equal to 1.
For Registers 0x24 and 0x25 to take effect, Bit 6 of register 0x1D must be set to 1.
DAC Channel A is the Sine output of the DDS and DAC Channel B is the Cosine
output of the DDS. Both outputs are therefore is quadrature.