Sundance SMT950 - Manual (Page 17)

Version 2.0 Page 17 of 52 SMT950 User Manual
Jumper J1 disables (position 1-2; also called External Clock Mode) or enables
(position2-3; also called Internal Clock Mode) the DAC internal PLL.
DAC output stage.
The following piece of schematics shows how the DAC outputs are coupled. The
DAC5687 generates differential output signals that are fed into an RF transformer
(Ohm ratio 4), that makes both DAC channels AC coupled. 100-Ohm resistors to Vcc
on the primary stage of the transformer allow balancing the secondary stage to 50
Ohm single-ended. (Note that R153 is not mounted).
Figure 7 - DAC Output Stage.
Clock Structure
There is one integrated clock generator on the module (CDCM7005 – Texas
instrument). The user can either use this clock (on-board) or provide the module with
an external clock (input via MMCX connector).