Sundance SMT942 - Manual (Page 45)

User Manual SMT942 Page 45 of 55 Last Edited: 23/08/2011 17:25:00
DAC Chab Register C 0x4C.
DAC Chab Register C 0x4C
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 Io_1p8_3p
3
Reserve
d
sleepb sleepa isbiaslpfb_
a
isbiaslpf_
b
Pll_sleep Pll_ena
Default ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ ‘1’ ‘0’ ‘1’
0 Reserved
Default ‘00000000’
DAC Chab Register C 0x4C
Setting Bit 8 Description pll_ena
0 ‘0’ Pll is off.
1 ‘1’ Pll is on and its output clock is used to clock the DAC.
Setting Bit 9 Description pll_sleep
0 ‘0’ Pll is not in sleep mode.
1 ‘1’ Pll is in sleep mode.
Setting Bit 10 Description isbiaslpf_b
0 ‘0’ Low pass filter for the current source bias in DACB is off.
1 ‘1’ Low pass filter for the current source bias in DACB is on. The low pass filter will set a
corner at 472Hz when low and 95KHz when high
Setting Bit 11 Description isbiaslpfb_a
0 ‘0’ Low pass filter for the current source bias in DACA is off.
1 ‘1’ Low pass filter for the current source bias in DACA is on. The low pass filter will set a
corner at 472Hz when low and 95KHz when high
Setting Bit 12 Description sleepa
0 ‘0’ DACA not in sleep mode.
1 ‘1’ DACA in sleep mode.
Setting Bit 13 Description sleepb
0 ‘0’ DACB not in sleep mode.
1 ‘1’ DACB in sleep mode.
Setting Bit 15 Description io_1p8_3p3
0 ‘0’ 3.3V tolerate pads
1 ‘1’ 1.8V tolerate pads
DAC Chab Register D 0x4D.
DAC Chab Register D 0x4D
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 Reserved
Default ‘00000000’