Dac chab register 0 0x40 – Sundance SMT942 User Manual
Page 38

User Manual SMT942
Page 38 of 55
Last Edited: 23/08/2011 17:25:00
DAC Chab Register 0 0x40.
DAC Chab Register 0 0x40
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Reserv
ed
Clk1_in_e
na
Clk1c_in_ena
Reserved Fir4_en qmc_offset_en
a
qmc_corr_en
a
mixer_en
a
Default
‘1’
‘1’
‘1’
‘0’
‘0’
‘0’
‘0’
‘0’
0
insel_mode
Reserved
Synchr_c
lkin
Twos
inv_clk
interp_value
Default
‘00’
‘0’
‘0’
‘0’
‘0’
‘00’
DAC Chab Register 0 0x40
Setting
Bit 1:0
Description interpolation value
0
00
1x.
1
01
2x.
2
10
4x.
3
11
8x.
Setting
Bit 2
Description inv_clk
0
0
Input clock not inverted.
1
1
Input clock inverted.
Setting
Bit 2
Description twos
0
0
Binary format
1
1
Two’s complement format.
Setting
Bit 2
Description synchr_clkin
0
0
Synchronous mode off.
1
1
Synchronous mode on. Clk1 and Clk2 must synchronous in phase and frequency when
reaching the DAC
Setting
Bit 7:6
Description insel mode
0
00
Normal input on Port A and Port B.
1
01
Interleaved input on Port A.
2
10
Interleaved input on Port B.
3
11
Half rate on Port A and B.
Setting
Bit 8
Description mixer_ena
0
0
Mixer bypassed.
1
1
Mixer enabled.
Setting
Bit 9
Description qmc_corr_ena
0
0
QMC phase and gain correction bypasses.
1
1
QNC phase and gain correction enabled.
Setting
Bit 10
Description qmc_offset_ena
0
0
QMC offset correction bypasses.
1
1
QNC offset correction enabled.
Setting
Bit 11
Description fir4_ena
0
0
Filter bypassed.
1
1
FIR4 Inverse Sinc filter enabled.