Clock register 2 0x12, Clock register 3 0x13 – Sundance SMT942 User Manual
Page 16
User Manual SMT942
Page 16 of 55
Last Edited: 23/08/2011 17:25:00
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Output0 (DAC chc&d clk1) Mode
PECLOHISWING
Reserved
Default
‘100000’
‘0’
‘0’
0
Reserved
ICP
CP_PRE
Reserved
Default
‘00’
‘0000’
‘0’
‘0’
Reset Register 1 0x11
Setting
Bit 1
Description CP_PRE - Preset charge pump output voltage to vcc/2
0
0
OFF.
1
1
ON.
Setting
Bit 5:2
Description ICP Charge pump current setting
0
0
1
1
Setting
Bit 9
Description PECL0HISWING PECL output voltage swing (DAC chc&d clk1)
0
0
Normal Operation.
1
1
High PECL output voltage.
Setting
Bit 15:10
Description Output0 (DAC chc&d clk1) mode
0
0
LVPECL only: ‘100000’.
CLOCK Register 2 0x12.
Clock Register 2 0x12
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Coarse Phase Adjustment[5:0] (Output DAC chc&d clk1 and clk2)
Reserved
Default
‘000000’
‘00’
0
Reserved
Reserved
Default
‘0011’
‘0001’
Reset Register 2 0x12
Setting
Bit 15:10
Description Coarse Phase Adjustment[5:0] DAC chc&d clk1 and clk2
0
0
1
1
CLOCK Register 3 0x13.
Clock Register 3 0x13
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Output0 (DAC chc&d clk2) Mode
PECL1HISWING
Output
Divider
Enable