Clock register 7 0x17, Clock register 8 0x18 – Sundance SMT942 User Manual
Page 19
User Manual SMT942
Page 19 of 55
Last Edited: 23/08/2011 17:25:00
0
‘00’
No current output reduction
1
‘01’
20% output current reduction
2
‘10’
30% output current reduction
Setting
Bit 15:10
Description Coarse Phase Adjustment[5:0] DAC cha&b clk1
0
0
1
1
CLOCK Register 7 0x17.
Clock Register 7 0x17
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Output0 (DAC cha&b clk2) Mode
PECL3HISWING
Output
Divider
Enable
Default
‘100000’
‘0’
‘0’
0
Output Divider Ratio DAC cha&b clk1 and clk2
Coarse Phase
Adjustment[6]
Default
‘0000000’
‘0’
Reset Register 7 0x17
Setting
Bit 0
Description - Coarse Phase Adjustment[6] DAC cha&b clk2
0
0
1
1
Setting
Bit 7:1
Description Output Divider Ratio DAC cha&b clk2
0
0
1
1
Setting
Bit 8
Description Output Divider Enable DAC cha&b clk2
0
0
Divider disabled.
1
1
Divider enabled.
Setting
Bit 9
Description PECL3HISWING PECL output voltage swing (DAC cha&b clk2)
0
0
Normal Operation.
1
1
High PECL output voltage.
Setting
Bit 15:10
Description Output3 (DAC cha&b clk2) mode
0
0
LVPECL only: ‘100000’.
CLOCK Register 8 0x18.
Clock Register 8 0x18
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
Coarse Phase Adjustment[5:0] (External Clock)
Reserved
HOLD_ON_LOR
Default
‘000000’
‘0’
‘0’
0
Reserved
Reserved