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Clock register 9 0x19, Clock register a 0x1a – Sundance SMT942 User Manual

Page 20

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User Manual SMT942

Page 20 of 55

Last Edited: 23/08/2011 17:25:00

Default

‘0000’

‘0011’

Reset Register 8 0x18

Setting

Bit 8

Description HOLD_ON_LOR

0

0

Normal mode of operation

1

1

Charge pump in tri-state mode

Setting

Bit 15:10

Description Coarse Phase Adjustment[5:0] External Clock

0

0

1

1


CLOCK Register 9 0x19.

Clock Register 9 0x19

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1

Output0 (External Clock) Mode

PECL4HISWING

Output

Divider

Enable

Default

‘100000’

‘0’

‘0’

0

Output Divider Ratio External Clock

Coarse Phase

Adjustment[6]

Default

‘0000000’

‘0’

Reset Register 9 0x19

Setting

Bit 0

Description - Coarse Phase Adjustment[6] External Clock

0

0

1

1

Setting

Bit 7:1

Description Output Divider Ratio External Clock

0

0

1

1

Setting

Bit 8

Description Output Divider Enable External Clock

0

0

Divider disabled.

1

1

Divider enabled.

Setting

Bit 9

Description PECL4HISWING PECL output voltage swing (External Clock)

0

0

Normal Operation.

1

1

High PECL output voltage.

Setting

Bit 15:10

Description Output4 (External Clock) mode

0

0

LVPECL only: ‘100000’.


CLOCK Register A 0x1A.

Clock Register A 0x1A

Byte

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0