Sundance SMT942 - Manual (Page 30)

User Manual SMT942 Page 30 of 55 Last Edited: 23/08/2011 17:25:00
2 10 2ns delay.
3 11 3ns delay.
Setting Bit 7:6 Description diffclk_dly
0 00 0ns delay.
1 01 1ns delay.
2 10 2ns delay.
3 11 3ns delay.
Setting Bit 8 Description - reva
0 0 Normal mode.
1 1 PortA reversed.
Setting Bit 9 Description revb
0 0 Normal mode.
1 1 PortB reversed.
Setting Bit 11 Description a_equals_b
0 0 Normal mode.
1 1 DACA driven by DACB data.
Setting Bit 12 Description b_equals_a
0 0 Normal mode.
1 1 DACB driven by DACA data
Setting Bit 14:13 Description - output_delay delay the output to both DACs
0 0 0 clock cycles
1 1 1 clock cycles
2 2 2 clock cycles
3 3 3 clock cycles
Setting Bit 15 Description ser_dac_data_ena
0 0 Normal mode of operation.
1 1 Muxes ser_dac_data to both DACs.
DAC Chab Register 2 0x32.
DAC Chab Register 2 0x32
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 Phase Offset [7:0]
Default ‘00000000
0 Sif4 Sif_sync
_sig
Clkdiv_syn
c_ena
Clkdiv_syn
c_sel
Reserve
d
Clkdiv_shift Mixer gain Reserved
Default ‘0’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’
DAC Chab Register 2 0x32
Setting Bit 1 Description Mixer gain
0 0 Nothing added.