Sundance SMT350 - Manual (Page 5)

Version 1.9 Page 5 of 45 SMT350 User Manual
Block of registers .................................................................................................... 41
Space available in FPGA ........................................................................................ 41
PCB Layout................................................................................................................. 42
Connectors ................................................................................................................. 44
Description .............................................................................................................. 44
Location on the board ............................................................................................. 45
Table of Figures
Figure 1 – Fan across PCI. ......................................................................................................7
Figure 2 - Block Diagram........................................................................................................10
Figure 3 - Main features. ........................................................................................................12
Figure 4 - ADC Input Stage. ...................................................................................................12
Figure 5 - DAC Output Stage. ................................................................................................14
Figure 6 - Clock Structure. .....................................................................................................14
Figure 7 - External Clock........................................................................................................16
Figure 8 - Clock Architecture Main Characteristics. ...............................................................17
Figure 9 – Mezzanine module Connector Interface (SLB data and power connectors).........18
Figure 10 – Mezzanine Module Interface Power Connector and Pinout. ...............................20
Figure 11 – Daughter Module Interface: Data Signals Connector and Pinout (Bank A). ......21
Figure 12 – Daughter Module Interface: Data Signals Connector and Pinout (Bank B). .......23
Figure 13 – Daughter Module Interface: Data Signals Connector and Pinout (Bank C). .......24
Figure 14 – Setup Packet Structure. ......................................................................................25
Figure 15 – Control Register Read Sequence. ......................................................................25
Figure 16 – Register Memory Map.........................................................................................27
Figure 17 - Firmware Block Diagram......................................................................................40
Figure 18 - Space available in FPGA .....................................................................................41
Figure 19 – Main Module Component Side............................................................................42
Figure 20 - Main Module (SMT368) Solder Side....................................................................42
Figure 21 - Daughter Module Component Side......................................................................43
Figure 22 - Daughter Module Solder Side..............................................................................43
Figure 23 - Connectors Location. ...........................................................................................45