Sundance SMT350 - Manual (Page 37)

Version 1.9 Page 37 of 45 SMT350 User Manual
Firmware Version – 0x1D
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Firmware Version
Default ‘00000000’
1 CDCM7005
Status
VCXO
CDCM7005
Status Ref
CDCM7005
Status Lock
Default ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’
DDS Register 0 – Start Phase Increment LSB - 0x20
DDS Register 0 – 0x20
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 DDS Start Phase Increment[15…8]
Default ‘00000000’
0 DDS Start Phase Increment [7…0]
Default ‘00000000’
DDS Register 1 – Start Phase Increment MSB - 0x21
DDS Register 1 – 0x21
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 DDS Start Phase Increment [31…24]
Default ‘00000000’
0 DDS Start Phase Increment [23…16]
Default ‘00000000’
The Start Phase Increment value is coded on 32 bits (DDS Data registers 0x20 and
0x21). Each value corresponds to a frequency generated worked out as follows:
Fout = Start Phase Increment * F
DAC sampling
(MHz) / 2
32
When the DDS is used in sweep mode, Start Phase Increment should be lower than
Stop Phase Increment
and Step Phase Increment should be greater than 0. When
used to generate a fixed frequency, Start Phase Increment should be equal to Stop
Phase Increment
and Step Phase Increment should be equal to 1.
For Registers 0x20 and 0x21 to take effect, Bit 4 of register 0x1D must be set to 1.
DAC Channel A is the Sine output of the DDS and DAC Channel B is the Cosine
output of the DDS. Both outputs are therefore is quadrature.
The Maximum Phase increment value supported by the design is 0x40000000, which
corresponds to a frequency of 30.72MHz when sampling at 122.88MHz with no
interpolation.