Sundance SMT350 - Manual (Page 17)

Version 1.9 Page 17 of 45 SMT350 User Manual
on option (3.3 V PECL).
Impedance 50-Ohm.
Frequency range 62.5 MHz maximum
Delay
External Ref. Input to Ext Ref. Out
External Clk Input to Ext Clk Out 9ns (between J29 and J4)
Figure 8 - Clock Architecture Main Characteristics.
Power Supply and Reset Structure
The SMT350 gets two power sources from the base module: 3.3 and 5 Volts. Linear
regulators are used to provide a clean and stable voltage supply to the analog
converters.
JumperJ1
There is one jumper (3 pin header) on the board. It is to control the power supply of
the DAC internal PLL. When fitted on positions 2 and 3, the PLL is enabled, whereas
on positions 1 and 2, it is disabled. Please refer to the DAC5686 datasheet for more
details.
Green LEDs.
There are 7 LEDs on the SMT350 Daughter Module. Five are dedicated for power
supplies monitoring: LED1 (1.8V DAC), LED2 (3.3V Clock), LED3 (3.3V DAC), LED4
(3.3V ADCA), LED6 (3.3V ADCB) should be all ON when the board is under power.
They state that power supplies all work fine.
LED5 (ADCs) should be flashing once the ADC Clocks are set up. It is actually a
divided version of ADCA sampling clock). LED7 (DAC) is a divided version of
PLLLOCK coming from the Dac (DAC5686).
Mezzanine module Interface
The daughter module interface is made up of two connectors (data and power). The
first one is a 0.5mm-pitch differential Samtec connector. This connector is for
transferring data such as ADC or DAC samples to and from the FPGA on the main
module. The second one is a 1mm-pitch Samtec header type connector. This
connector is for providing power to the daughter-card.
Sundance defines these two connectors as the Sundance LVDS Bus (SLB). It has
originally been made for data transfers using LVDS format but can also be used with
single-ended lines, which is the case for the SMT350. To know more about the SLB,
please refer to
the SLB specifications .