Sundance SMT350 - Manual (Page 27)

Version 1.9 Page 27 of 45 SMT350 User Manual
0x24 DDS Register 4 – Step Phase Increment LSB Read-back (FPGA Register) DDS Register 4.
0x25 DDS Register 5 – Step Phase Increment MSB Read-back (FPGA Register) DDS Register 5.
Figure 16 – Register Memory Map.
Register Descriptions
Reset Register – 0x0.
Reset Register – 0x0
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Reserved Reserved DDS
Reset
PHSTR CDCM7005
Reset
DAC Reset ADCs
Reset
Default ‘0’ ‘0’ ‘1’ ‘00’ ‘1’ ‘1’ ‘1’
Reset Register – 0x0
Setting Bit 0 Description
0 0 Normal Operation.
1 1 Resets both ADC devices as well as their corresponding Serial Interfaces.
Setting Bit 1 Description
0 0 Normal Operation.
1 1 Resets both DAC device as well as its Serial Interfaces.
Setting Bit 2 Description
0 0 Normal Operation.
1 1 Resets both CLK device as well as its Serial Interfaces.
Setting Bit 4&3 Description
0 00 Normal Operation – DAC PHSTR is Tri-Stated.
1 01 DAC PHSTR line is driven High.
2 10 DAC PHSTR line is driven Low.
3 11 Normal Operation – DAC PHSTR is Tri-Stated.
Setting Bit 5 Description
0 0 DDS Activated and SHB put on hold.
1 1 Resets DDS Core (SHB samples are routed to the DAC)
Note 1: What is mentioned as DAC PHSTR line is the physical net on the board that
connects together the FPGA to the PHSTR pin (DAC5686) as well as to J5 (+). In a
multiple board system, one board can be used as a master and its PHSTR pin can
be driven high or low and an other one as slave, in which case its DAC PHSTR pin
must be tri-stated.
Note 2: The Reset bits don’t get cleared automatically, so a device can remain reset
while not used to reduce the global power consumption.