Zilog EZ80L92 - Manual (Page 80)

eZ80L92 Development Kit
User Manual
General Array Logic Equations UM012913-0407
76
nmemen2,
nmemen3,
nmemen4
);
input
nFL_DIS /* synthesis loc="P4"*/,
nCS0 /* synthesis loc="P5"*/,
nCS2 /* synthesis loc="P3"*/, //was 23
A7 /* synthesis loc="P6"*/,
A6 /* synthesis loc="P7"*/,
A5 /* synthesis loc="P9"*/,
A4 /* synthesis loc="P10"*/,
A3 /* synthesis loc="P11"*/,
A2 /* synthesis loc="P12"*/,
A1 /* synthesis loc="P13"*/,
A0 /* synthesis loc="P16"*/,
nEX_FL_DIS /* synthesis loc="P2"*/;
//input[7:0] A; upper part of Address Bus of L92
//A23=A7,A22=A6,A21=A5,A20=A4,A19=A3
//A18=A2,A17=A1,A16=A0
output
nCS_EX /* synthesis loc="P17"*/, //enables memory on the
//Expansion Module
nmemen1 /* synthesis loc="P18"*/, //enables memory on the
//Development Platform
nmemen2 /* synthesis loc="P19"*/,
nmemen3 /* synthesis loc="P20"*/,
nmemen4 /* synthesis loc="P21"*/,
nEM_EN /* synthesis loc="P24"*/, //enables LED and the
//general-purpose port.
nDIS_FL /* synthesis loc="P25"*/,
nL_RD /* synthesis loc="P23"*/
;