Zilog EZ80L92 - Manual (Page 74)

UM012913-0407 Schematic Diagrams
eZ80L92 Development Kit
User Manual
70
Figure 26. eZ80L92 Module Schematic Diagram, #5 of 9—E-NET Module
device addresses:
00300h bis 0030Fh
TX+ <-> 1
TX- <-> 2
RX+ <-> 3
RX- <-> 6
=
int. Pull-Up
yellow
90 degree,
stacked
dual-LED
ESD protection array
green
place
near
J1
through hole
solder pad
don’t stuff
don’t
stuff
VSS
VDD
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7
SD[0..7]
SA0
SA1
SA2
SA3
TD-
RXD- RD-
TXD-
TXD+
RXD+
SA[0..3]
RXD-
RXD+
TXD-
TXD+
CTD
CRD
ETHIRQ
ETHIRQ
-ETHWR -ETHWR
-SLEEP
-LANLED -ACTIVE
SD[0..7]
SA[0..3]
-SLEEP
-LANLED
-LINKLED
-ETHRD
-ETHRD
TD+
RD+
RD+
-LINKLED
RD- TD-
-LANLED
TD+
VDD
VSS CASE
V3.3
GND
GND GND
V3.3
GND
C15
100nF
U7
CS8900A-CQ3
TQFP100
71 72 73 74 65 66 67 68 58 59 60 51 52 53 54
37
1
38
2
39
3
40
4
41
5
42
6
43
7
44
8
45
9
46
10
47
11
48
12
49
13
50
14 15 16 17 18 19 20 21 22 23 24 25
26
27
28
29
30
31
32
33
34
35
36
55 56 57 61 62 63 64 69 70 75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SD4 SD5 SD6 SD7 SD0 SD1 SD2 SD3 SA17 SA18 SA19 SA13 SA14 SA15 SA16
SA0
AVSS
SA1
ELCS
SA2
EECS
SA3
EESK
SA4
EEDATAOUT (TDO)
SA5
EEDATAIN
SA6
CHIPSEL
SA7
DVSS
SA8
DVDD
SA9
DVSS
SA10
DMARQ2
SA11
DMACK2
REFRESH
DMARQ1
SA12
DMACK1 DMARQ0 DMACK0
CSOUT
SD15 SD14 SD13 SD12
DVDD DVSS SD11 SD10
SD9
SD8
MEMW
MEMR
INTRQ2
INTRQ1
INTRQ0
IOCS16
MEMCS16
INTRQ3
SHBE
DVSS DVDD DVSS IOR IOW AEN (TCK) IOCHRDY DVDD DVSS RESET
TEST
SLEEP
BSTATUS/HC1
DI+
DI-
CI+
CI-
DO+
DO-
AVDD
AVSS
TXD+
TXD-
AVSS
AVDD
RXD+
RXD-
RES
AVSS
AVDD
AVSS
XTAL1
XTAL2
LINKLED/HC0
LANLED
R26
100
R24
8R2
U9
LCDA15C-6
SO8.150
1
2
3
4 5
6
7
8
R25 8R2
C12
560pF
Y1
20.000 MHz
HC49SM
R23
4k99/1%
R22
4k7
R19
10k
J1
HFJ11-1041
HALOFASTJACK
1
2
3
4
5
6
8
1
2
3
4
5
6
8
C13
100nF
LD1B
4 3
L2
ferrite
tbd
JP4
HEADER 1
SIP1
1
R34
10k
0603
LD1A
2 1
R20
220
0603
R21
220
0603
C14
100nF
ETHIRQ
-ETHWR
-ACTIVE
-SLEEP
SA[0..3]
SD[0..7]
-ETHRD
IOCHRDY
-DIS_ETH