Zilog EZ80L92 - Manual (Page 27)

eZ80L92 Development Kit
User Manual
UM012913-0407 Operational Description
23
I/O Functionality
The eZ80Acclaim! ® Development Platform provides additional functional-
ity, featuring general-purpose port, an LED matrix, a modem reset, and two
user triggers. These functions are memory-mapped with an address decoder
based on the Generic Array Logic GAL22lV10D (U15) device manufac-
tured by Lattice Semiconductor, and a bidirectional latch (U16). Addition-
ally, U15 is used to decode addresses for access to the 7 x 5 LED matrix.
Table 6 lists the memory map addresses to registers that allow access to
the above functions. The register at address
800000h
controls general-
purpose port output control and LED anode register functions. The register
at address
800001h
controls the register functions for the LED cathode,
modem reset, and user triggers. Address
800002h
controls general-pur-
pose port data.
BUSACK 37 CPU Bus Acknowledge Signal Output
NMI 39 Nonmaskable Interrupt Input
D[0:7] 43–50 Data Bus Bidirectional
CS[0:3] 53–56 Chip Selects
MEMRQ 57 Memory Request Output
WR 34 WRITE Signal Output
INSTRD 36 Instruction Fetch Output
BUSREQ 38 CPU Bus Request signal
PHY 40 Clock output of the CPU Output
Table 5. CPU Bus Connector J8* (Continued)
Signal Pin No. Function Direction
Note: All the signals except BUSACK and INSTRD are driven by low-voltage CMOS technology
(LVC) drivers.