Zilog EZ80L92 - Manual (Page 16)

eZ80L92 Development Kit
User Manual
Operational Description UM012913-0407
12
Table 2. eZ80Acclaim! ® Development Platform Peripheral Bus Connector
Identification—JP1 1
Pin No. Symbol Signal Direction Active Level eZ80L92 Signal
2
1 A6 Bidirectional Yes
2 A0 Bidirectional Yes
3 A10 Bidirectional Yes
4 A3 Bidirectional Yes
5 GND
6 V
DD
7 A8 Bidirectional Yes
8 A7 Bidirectional Yes
9 A13 Bidirectional Yes
10 A9 Bidirectional Yes
11 A15 Bidirectional Yes
12 A14 Bidirectional Yes
13 A18 Bidirectional Yes
14 A16 Bidirectional Yes
15 A19 Bidirectional Yes
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80L92 Module Schematics. see
eZ80L92 Module .
2. The Power and Ground nets are connected directly to the eZ80L92 device.
Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be
below 10 pF to satisfy the timing requirements for the eZ80
®
CPU. All unused inputs should be
pulled to either V
DD
or GND, depending on their inactive levels to reduce power consumption and
to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80L92’s Peripheral Power-Down Register.