Zilog EZ80L92 User Manual
Page 19
eZ80L92 Development Kit
User Manual
UM012913-0407
Operational
Description
15
46
RD
Bidirectional
Low
Yes
47
WR
Bidirectional
Low
Yes
48
INSTRD
Input
Low
Yes
49
BUSACK
Input
Pull-Up 10 K
Ω
; Low
Yes
50
BUSREQ
Output
Pull-Up 10 K
Ω
; Low
Yes
Table 2. eZ80Acclaim!
®
Development Platform Peripheral Bus Connector
Identification—JP1
1
(Continued)
Pin No.
Symbol
Signal Direction
Active Level
eZ80L92 Signal
2
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80L92 Module Schematics. see
eZ80L92 Module
.
2. The Power and Ground nets are connected directly to the eZ80L92 device.
Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be
below 10 pF to satisfy the timing requirements for the eZ80
®
CPU. All unused inputs should be
pulled to either V
DD
or GND, depending on their inactive levels to reduce power consumption and
to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80L92’s Peripheral Power-Down Register.