Zilog EZ80L92 User Manual
Page 35
eZ80L92 Development Kit
User Manual
UM012913-0407
Operational
Description
31
vides this capability. However, you should be aware that additional
SRAM must be installed in the following order:
1. U19, address range
B00000h
–
B7FFFFh
2. U18, address range
A80000h
–
AFFFFFh
3. U17, address range
A00000h
–
A7FFFFh
If SRAM memory is installed in a different order than the above
sequence, SRAM will not be contiguous unless the user is able to change
the address decoder, U10. Memory access decoding is performed by this
address decoder, implemented in the Generic Array Logic device,
GAL22LV10D (U10).
Flash Memory
The eZ80L92 Development Kit allows Flash memories between 1 MB
and 4 MB. The chips are housed in wide TSOP40 cases. Flash ROM
access times are 55–150 ns; typically 90 ns.
When accessing Flash memory, the eZ80L92 device should be configured
to operate in Intel bus mode to satisfy setup and hold times and to prevent
bus contention with a Write cycle that could possibly follow. For proper
CPU operation at 48 MHz, first set the bus mode control register
CS0_BMC (I/O address
F0h
) to
82h
, then set the Chip Select Control
register CS0_CTL (I/O address
AAh
) to
08h
. These settings select Intel
Bus Mode with two system clocks per bus cycle and zero wait states.
Memory Map
A memory map of the eZ80
®
CPU is illustrated in
. Flash mem-
ory and SRAM on the eZ80L92 Module are addressed when CS0 and CS1
are active Low. SRAM on the eZ80Acclaim!
®
Development Platform is
addressed when CS2 is active Low.
The Ethernet controller located on the eZ80L92 Module, is mapped as an
I/O device at address
300h
. It uses CS3.
Note: