Altera Transceiver Signal Integrity - Manual (Page 29)

Chapter 6: Board Test System 6–5
Using the Board Test System
February 2013 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix V GT Edition User Guide
■ PSR —Sets the MAX II PSR register. The numerical values in the list corresponds to
the page of flash memory to load during FPGA reconfiguration. Refer to Table 6–1
for more information.
■ PSS —Displays the MAX II PSS register value. Refer to Table 6–1 for the list of
available options.
1 Because the System Info tab requires that a specific design is running in the FPGA at
a specific clock speed, writing a 0 to SRST or changing the PSO value can cause the
Board Test System to stop running.
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain. The
Stratix V GT device is always the first device in the chain.
1
When set to 0, switch S7.6 (MAX BYPASS) includes the MAX II device in the JTAG
chain; when set to 1, the MAX II device is removed from the JTAG chain.
Qsys Memory Map
The Qsys memory map control shows the memory map of the Qsys system on your
board.