Altera Partial Reconfiguration IP Core User Manual
Page 26
my_freeze_region_A (
.freeze(freeze_A_w),
…
);
// Freeze wrapper for input signals of single PR region B
// Follow existing recommendations in the PR user guide for the details
freeze_region_B my_freeze_region _B (
.freeze(freeze_B_w),
…
);
endmodule
Related Information
For more information on creating a freeze wrapper for partial reconfiguration.
Sample PR IP Core as an External Host on the Same Device
There are occasions where you should instantiate the PR IP core as external host on the same device.
1. To monitor the
prblock
and
crcblock
WYSIWYG interface signals using the SignalTap II tool or to
probe these signals by routing them to any GPIO.
2. To share the
prblock
and
crcblock
WYSIWYG interface signals with another IP. For example, using
the Fault Injection IP or a user controller to unload the Error Message Register (EMR) when a
CRC_ERROR
is asserted.
The following Verilog HDL pseudocode shows an example of how to instantiate the PR IP core as external
host on the same device.
// pseudocode for instantiating the PR IP core as ExternalHost
// on the same device
module design_top (…);
// PR IP core instantiated as External Host
alt_pr_sv my_alt_pr (
.pr_request_pin (pr_request_w),
.pr_ready_pin (pr_ready_w),
.pr_done_pin (pr_done_w),
.pr_error_pin (pr_error_w),
.pr_clk_pin (pr_clk_w),
.pr_data_pin (pr_data_w),
.crc_error_pin (crc_error_w),
...
);
// Stratix V prblock WYSIWYG
stratixv_prblock my_prblock (
.clk (pr_clk_w),
.corectl(1'b1), // note that this design still PR from core
.prrequest (pr_request_w),
.data (pr_data_w),
.error (pr_error_w),
.ready (pr_ready_w),
.done (pr_done_w)
);
// Stratix V crcblock WYSIWYG
stratixv_crcblock my_crcblock (
.crcerror(crc_error_w),
…
);
endmodule
26
Sample PR IP Core as an External Host on the Same Device
UG-PARTRECON
2015.05.04
Altera Corporation
Partial Reconfiguration IP Core