Altera Partial Reconfiguration IP Core - Manual

Partial Reconfiguration IP Core
2015.05.04
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Partial reconfiguration (PR) is fully supported in the Stratix ® V device family, which offers you the ability
to reconfigure part of the design's core logic such as LABs, MLABs, DSP, and RAM, while the remainder
of the design continues running. The PR IP core can be implemented through the Qsys Interface, or via
the Quartus II ® IP Catalog.
Partial reconfiguration is performed through either an internal host residing in the core logic or as an
external host via dedicated PR pins. The advantage of the internal host is that you can store all the logic
needed for PR on the device, without the need for external devices.
Figure 1: PR IP core Components
When you instantiate the PR IP core, the Main Controller module which includes the Control Block
Interface Controller, Freeze/Unfreeze Controller, and the Data Source Controller are all instantiated. A
Data Source Interface module provides you with a JTAG Debug Interface and PR Data Interface. If you
choose to use the PR IP core as an internal host, it automatically instantiates the corresponding
crcblock
and
prblock
WYSIWYG atom primitives.
CRCBLOCK PRBLOCK
CB Interface Controller
Freeze/Unfreeze Controller
Data Source Controller
JTAG Debug
Interface
PR Data
Interface
FPGA Control
Block (CB)
Interface Module
Main Controller
Module
(1)
PR Data Source
Interface Module
Note:
1. The main controller module handles all the handshaking signals of the
CB interface and processes the incoming data, as needed, before sending
to the PRBLOCK. It also handles the freeze/un-freeze PR interface.
If it is used as external host (placed in another FPGA or CPLD), the PR IP core provides the
crcblock
and
prblock
WYSIWYG atom primitive as interface ports so that you can connect to the dedicated PR
pins and
CRC_ERROR
pin on the target FPGA undergoing partial reconfiguration.
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