Altera Partial Reconfiguration IP Core - Manual (Page 19)

The PR data interface provides you with selectable input data width;
x1
,
x2
,
x4
,
x8
,
x16
, and
x32
. It can be
connected to
ASMI_PARALLEL
as well as the Avalon interface to obtain PR data from on-chip RAM,
external flash device, or PR over PCIe.
If the input data width is other than
x16
, the PR IP core includes a data upsize or downsize module so
that the data output to the Data Source Controller is always
x16
.
JTAG Debug Mode for Partial Reconfiguration
The JTAG debug mode allows you to configure partial reconfiguration bitstream through the JTAG
interface. Use this feature to debug PR bitstream and eventually helping you in your PR design
prototyping. This feature is available for internal and external host.
During JTAG debug operation, the JTAG command sent from the Quartus II Programmer ignores and
overrides most of the Partial Reconfiguration IP core interface signals (
clk
,
pr_start
,
double_pr
,
data[]
,
data_valid
, and
data_read
).
Note: The
TCK
is the main clock source for PR IP core during this operation.
You can view the status of Partial Reconfiguration operation in the messages box and the Progress bar in
the Quartus II Programmer. The
PR_DONE
,
PR_ERROR
, and
CRC_ERROR
signals will be monitored during PR
operation and reported in the Messages box at the end of the operation.
The Quartus II Programmer can detect the number of
PR_DONE
instruction(s) in plain or compressed PR
bitstream and, therefore, can handle single or double PR cycle accordingly. However, only single PR cycle
is supported for encrypted Partial Reconfiguration bitstream in JTAG debug mode (provided that the
specified device is configured with the encrypted base bitstream which contains the PR IP core in the
design).
Note: Configuring an incompatible PR bitstream to the specified device may corrupt your design,
including the routing path and the PR IP core placed in the static region. When this issue occurs,
the PR IP core stays in an undefined state, and the Quartus II Programmer is unable to reset the IP
core. As a result, the Quartus II Programmer generates the following error when you try to
configure a new PR bitstream:
Error (12897): Partial Reconfiguration status: Can't reset the PR megafunction.
This issue occurred because the design was corrupted by an incompatible PR
bitstream in the previous PR operation. You must reconfigure the device with a good
design.
Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
To configure the Partial Reconfiguration bitstream in JTAG debug mode, follow these steps:
1. In the Quartus II Programmer GUI, right click on a highlighted base bitstream (in .sof) and then click
Add PR Programming File to add the PR bitstream (.rbf).
UG-PARTRECON
2015.05.04
JTAG Debug Mode for Partial Reconfiguration 19
Partial Reconfiguration IP Core Altera Corporation
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