Altera Arria V SoC - Manual (Page 37)

Chapter 5: Board Test System 5–17
The Clock Control
June 2014 Altera Corporation Arria V SoC Development Kit
User Guide
U60— FPGA Power Monitor 1
U50— FPGA Power Monitor 2
They display the mA power consumption of your board over time.
The green line indicates the current value. The red line indicates the maximum value
read since the last reset.
1 You can enlarge a graph by clicking on it. Click it again to restore the original size.
Temp on 2977
The temperature controls display only the temperature from the power supply
manager, not the FPGA.
Total Power
These controls display the sum of all four rails for each group, U34 and for U26.
Controls
This group contains the following controls:
■ Start —Starts the communication with the board to monitor power.
■ Stop —Stops the communication with the board to monitor power.
■ Update speed —Specifies how often to refresh the graph.
■ Log Results —Specifies that a log file is saved to
dir>\kits\arriaVST_5astfd5kf40es_soc\examples\board_test_system.
■ MAX V version —Indicates the version of MAX V code currently running on the
board. The MAX V code resides in the dir>\kits\arriaVST_5astfd5kf40es_soc\factory_recovery and dir>\kits\arriaVST_5astfd5kf40es_soc\examples\max5 directories.
1 Newer revisions of this code might be available on the Arria V SoC
Development Kit page of the Altera website.
f A table with the power rail information is available in the Arria V SoC Development
Board Reference Manual .
The Clock Control
The Clock Control application sets the Si570 (X2), Si571 (X3), or Si5338 (U31)
programmable oscillators to any frequency between 10 MHz and 810 MHz. The
frequencies support eight digits of precision to the right of the decimal point.
The Clock Control application runs as a stand-alone application. ClockControl.exe
resides in the dir>\kits\arriaVST_5astfd5kf40es_soc\examples\board_test_system directory.
To start the application, click Start > All Programs > Altera >
Arria V SoC Development Kit
<version> > Clock Control.