Altera Arria V SoC - Manual (Page 35)

Chapter 5: Board Test System 5–15
Using the Board Test System
June 2014 Altera Corporation Arria V SoC Development Kit
User Guide
■ Detected errors —Displays the number of bit errors detected by the error checking
circuitry.
■ BER —Displays the bit error rate of the interface.
■ PLL lock —Displays Yes if the SDI PLL is locked.
■ Pattern sync —Displays Yes if the receiver has detected the input data pattern.
■ Start— Starts the PRBS data test and begins to monitor and update screen with
live test results.
■ Stop —Stops the PRBS data test.
■ Insert Error —Inserts an error into an SDI data stream that is detected by the
receiver when in loopback using the included video cable.
■ Clear —Clears the Detected errors counter.
■ PMA Setting —Opens the PMA settings window that allows for adjusting the
analog transceiver settings, such as output voltage, loopback settings, and
equalization.
■ PRBS (list)—Selects the transmit pattern and sets the receive error detection
circuitry to expect the same pattern for use in loopback testing.