The xcvr tab, Sfp a, sfp b, sma, The xcvr tab –10 – Altera Arria V SoC User Manual
Page 30: Sfp a, sfp b, sma –10

5–10
Chapter 5: Board Test System
Using the Board Test System
Arria V SoC Development Kit
June 2014
Altera Corporation
User Guide
The XCVR Tab
The XCVR tab allows you to perform loopback tests on the SFP A, SFP B, and SMA
ports.
Figure 5–6
shows the XCVR tab.
1
To perform these tests you need:
■
Two SFP optical or metal loopback cables to test both at the same time
■
Two matching SMA cables for the SMA loopback
The following sections describe the controls on the XCVR tab.
SFP A, SFP B, SMA
These groups displays the following SFP A, SFP B, SMA status information during the
loopback test:
■
Data rate
—Displays the current SFP A, SFP B, SMA data rate in megabytes per
second (MBps).
■
Freq
—Displays the data rate frequency in MHz which is equivalent to MBps.
Figure 5–6. The XCRV Tab
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)