Altera Nios II C2H Compiler User Manual
Page 99

Altera Corporation
9.1
4–5
November 2009
Nios II C2H Compiler User Guide
Understanding the C2H View
Example 4–1. Vector Power Calculation
#pragma altera_accelerate connect_variable power_calculation/voltage to onchipRAM1
#pragma altera_accelerate connect_variable power_calculation/current to onchipRAM1
#pragma altera_accelerate connect_variable power_calculation/power to onchipRAM2
void power_calculation ( short * _ _ restrict_ _ voltage,
short * _ _ restrict_ _ current,
short * _ _ restrict_ _ power,
short downscale,
int length)
{
int i;
for(i = 0; i < length; i++)
{
*power++ = (*voltage++ * *current++) >> downscale;
}
}
requires Avalon-MM read and write master ports to
perform memory accesses. It also requires a multiplier and a barrel shifter
to perform the right shift operation. The pragma statements inform the
C2H Compiler that the input data is stored in a memory called
onchipRAM1
and the output data is to be stored in
onchipRAM2
. When
the C2H Compiler compiles this function, the Nios II IDE generates a
build report as shown in
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)