The c2h compiler operates at the function level – Altera Nios II C2H Compiler User Manual
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9.1
Altera Corporation
Nios II C2H Compiler User Guide
November 2009
C2H Compiler Concepts
The C2H Compiler Operates at the Function Level
Code you want to accelerate must be expressed as an individual C
function. The C2H Compiler converts all code within and below the
chosen function to a hardware accelerator block. If the function you are
accelerating calls a subfunction, the C2H Compiler also converts the
subfunction to a hardware accelerator. Therefore, you must be careful that
subfunctions are also good candidates for C2H acceleration.
If the code you want to accelerate is not isolated in a separate function, a
good practice is to partition the function to separate the critical section
into its own function. The resulting hardware accelerator then replaces
only processor-intensive tasks, rather than setup or control tasks which
the processor can implement efficiently.
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
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- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
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- DCFIFO (28 pages)