Altera Nios II C2H Compiler - Manual (Page 82)

3–42 9.1 Altera Corporation
Nios II C2H Compiler User Guide November 2009
Scheduling
Memory Transfers
Avalon-MM system interconnect fabric manages arbitration between
multiple Avalon-MM master ports that access a single slave port. A
master port might have to wait several clock cycles before beginning a
transfer due to arbitration. If a master port on an accelerator is being
forced to wait, the state machine for the accelerator stalls until the transfer
can proceed.
Loop Pipelining
The C2H Compiler structures the state machine for a loop so that
iterations of the loop are pipelined. In other words, consecutive iterations
of the loop can begin before prior iterations have completed.
Pipelining Loop Iterations
Figure 3–20 shows the dependency graph for the loop block in
Example 3–35 .
Example 3–35. Loop Block
int mac(int *data_array, int *coef_array, int len)
{
int sum = 0;
do
{
int x = *data_array++;
int c = *coef_array++;
int prod = c * x;
sum += prod;
} while (i++ < len);
return sum;
}