Altera Nios II C2H Compiler User Manual
Page 58

3–18
9.1
Altera Corporation
Nios II C2H Compiler User Guide
November 2009
Memory Accesses
shows two dereferences that are identical inside of a loop.
The C2H Compiler consolidates them into a single master port.
Example 3–10. Equivalent Pointers in a Loop
void equivalent_pointers(char *packed_data, int len)
{
int i = 0;
while (i < len)
{
char ms_nibble = *(packed_data) >> 4;
char ls_nibble = *(packed_data++) & 0x0f;
...
i++;
}
}
demonstrates a case of non equivalent pointers.
, but
packed_data
increments
between the two pointer dereferences. In this case the address
expressions have different values, which translate to two separate master
ports.
Example 3–11. Nonequivalent Pointers
void nonequivalent_pointers(char *packed_data, int len)
{
int i = 0;
while (i < len)
{
char ms_nibble = *(packed_data++) >> 4;
char ls_nibble = *(packed_data) & 0x0f;
...
i++;
}
}
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)