Avalon-mm master port signal generation – Altera Nios II C2H Compiler User Manual
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3–20
9.1
Altera Corporation
Nios II C2H Compiler User Guide
November 2009
Memory Accesses
volatile
to guarantee multiple,
distinct reads from a constant address.
Example 3–13. volatile Type Qualifier
volatile char *DataFIFO = FIFO_BASE;
char Byte0 = *DataFIFO;
char Byte1 = *DataFIFO;
char Byte2 = *DataFIFO;
char Byte3 = *DataFIFO;
By comparison,
demonstrates two sections of code that are
equivalent, due to the consolidation of equivalent pointers. In this case,
the type of
*DataFIFO
is not declared
volatile
.
Example 3–14. Equivalent Pointers
char *DataFIFO = FIFO_BASE;
char Byte0 = *DataFIFO;
char Byte1 = *DataFIFO;
char Byte2 = *DataFIFO;
char Byte3 = *DataFIFO;
// The code above is equivalent to the following:
char *DataFIFO = FIFO_BASE;
char dereferenced_DataFIFO = *DataFIFO;
char Byte0 = dereferenced_DataFIFO;
char Byte1 = dereferenced_DataFIFO;
char Byte2 = dereferenced_DataFIFO;
char Byte3 = dereferenced_DataFIFO;
Avalon-MM Master Port Signal Generation
A dereference operation, such as
*(ptr_to_int + i)
, translates to an
Avalon-MM master port on the accelerator. This section describes how
hardware accelerator logic generates the signals that drive the master
port.
Avalon-MM master ports created by the C2H Compiler comprise the
following fundamental elements:
■
Logic to compute the address signal
■
For write transfers only, logic to compute the write-data signal
■
Logic to control the read-enable or write-enable signal